1. Field of the Invention
The present invention relates to a semiconductor memory device namely a stacked capacitor type dynamic random access memory (DRAM) having a field shield separation structure and to a method of manufacturing the same.
2. Description of the Related Art
FIGS. 1A to 1D illustrate a method of manufacturing a conventional stacked capacitor type DRAM having the field shield separation structure. In the method, as shown in FIG. 1A, a silicon oxide layer 12, a conductive thin film layer 13 and an insulating layer 14 are successively formed on the whole surface of a silicon substrate 11.
Thereafter, portions of the insulating layer 14, the conductive thin film layer 13 and the silicon oxide layer 12 in an element forming area 15 are removed and only portions thereof in a field area 16 are left. In the process described up to now, a field shield separation structure having the conductive thin film layer 13 as a shield electrode can be formed.
Then, as shown in FIG. 1B, a gate insulating layer 17 is formed on the surface of the element forming area 15 and a gate electrode 18 is patterned on the gate insulating layer 17 and on the insulating layer 14. Then, a source and drain 21 are formed on both sides of the gate electrode 18 in the element forming area 15 to complete a transistor 22 of a memory cell. Thereafter, as shown in FIG. 1C, an insulating layer 23 is deposited on the whole surface and an opening 24 is formed in the insulating layer 23 and the gate insulating layer 17 to reach one of the source and drain 21.
Then, as shown in FIG. 1D, a lower electrode 25 of a capacitor is patterned to come into contact with one of the source and drain 21 through the opening 24, and a capacitor dielectric layer 26 and an upper electrode 27 are further formed to complete the capacitor 28 of the memory cell. A fixed voltage is applied to the conductive thin film layer 13 constituting the shield electrode to suppress conduction of a parasitic metal-oxide-semiconductor (MOS) transistor in the field area 16.
In the conventional device manufactured above, as apparent from FIG. 1D, the insulating layers 14 and 23 having a total thickness of 200 to 400 nm are interposed between the conductive thin film layer 13 serving as the shield electrode and the lower electrode 25 of the capacitor 28. Accordingly, a capacitance of the capacitor 28 produced by a potential difference between the conductive thin film layer 13 and the lower electrode 25 is of an almost negligible value.
Consequently, a capacitance of the capacitor 28 is restricted by a sum of areas of the upper surface and the side of the lower electrode 25, that is, a sum of areas of the lower electrode 25 and the upper electrode 27 opposite to each other through the capacitor dielectric layer 26. Accordingly, it is necessary to increase the area of the memory cell in order to increase its capacitance and hence it is difficult to attain the high level of integration.